Improved Flicker Noise Model for Submicron MOSFET devices

The generation of additional interface traps in the pinch-off region and the threshold voltage shift due to hotelectron stressing have been shown to cause 1-3 orders of magnitude increase in the flicker noise density. This flicker noise “overshoot” can easily degrade the performance/resolution of analog circuits by 6-18dB. An improved flicker noise model which is capable of accurately predicting the 1/f noise characteristics of submicron MOSFET devices over a wide range of gate bias, and for various device sizes and hot-carrier stressing conditions has been developed. The functional form of the improved model takes into account both carrier number fluctuation and surface mobility fluctuation, and is similar to the BSIM3v3.1 model, with the exception that the improved model accounts for hot-carrier stressing effects. Excellent agreement between the improved model and measured data for devices fabricated in a 0.35μm standard CMOS process was observed.